One of the most expensive steps in fabrication of a multi-layered printed circuit board is formation of an electrical conductor (sometimes called via) between the layers by drilling a via hole through the layers and plating the via hole with a conductive layer.
One desirable characteristic of a via in a printed circuit board is smaller size that permits larger number of traces to be formed in a printed circuit board of a given area. Conventional drilling process is mechanical. As the size of the via hole to be drilled becomes smaller, the drill bit size decreases and the cost of making a small and precise drill bit goes up. Additionally, the low mechanical strength of a small drill bit causes faster wear as compared to a large drill bit.
Therefore the cost of mechanically drilling a small hole increases exponentially with decreasing hole size. Another disadvantage of mechanical drilling is that a drill bit wears out after being used a number of times.
The mechanical drilling process needs a target area (sometimes called "land") that is larger than the drill bit's size, to account for possible misalignment during drilling. The diameter of the land is typically 10 to 15 mils larger than the drill bit diameter. The space used to satisfy the land requirement also substantially limits the number of traces that can be formed in a given area. For typical state of the art processing, where a conductive line (also referred to as "trace" or "electrode") and space have widths 3 mils/3 mils respectively, the via holes diameter is 8 mils, with 13 to 15 mils diameter in land space.
Another problem with mechanical drilling is that a conductive layer must be plated inside the via hole. The smaller the via hole, the larger the aspect ratio between the layer's thickness and the drill's hole diameter, and the more difficult it is to plate the via hole.
A method to inexpensively reduce the via hole's size and create a reliable conductive path in the via hole is highly desirable.
A laser method, by focusing the energy from a laser beam, can create a very small hole having a diameter for example in 1 to 2 mil range. The laser method avoids the problem of drill bit wear. However the laser method is expensive, and the hole's size and the impact on the material are not reproducible. Also the initial setup cost of the laser method is very high.
Another approach is to etch vias with a dry etch process. A large number of vias can be etched simultaneously, which eliminates the drill bit wear problem. In the dry etch method, a thin polyimide layer with copper foils laminated on each side is used as the starting core layer. Photoresist is applied on both sides to define photo via holes. After chemical copper etching and resist stripping, polyimide inside the original photo via hole (where the copper is already removed) is exposed to plasma. After the polyimide is etched away inside the via hole, a metallization step is performed to coat an electrically conductive layer inside the via hole. Another photo masking and etch step is performed to create conductive trace patterns (e.g. of copper) on both sides of the core layer and with vias connecting traces from each side of the core layer.
The dry etch process also has several disadvantages. Alignment/registration tolerance is high as two images from each side must coincide. Without such alignment, the created via hole could have a zig-zagged shaped surface that is unreliable after metallization. The laminate must be very thin as a plasma etch takes very long time (as compared to other printed circuit board processes). The substrate material may be limited to polyimide, as the heat generated in the dry etch is high and thermal mismatch between substrate and copper could create buckling or delamination.
Another alternative to the mechanical drilling process is use of a photoresist process to create a small via hole, e.g. 2 mils in diameter. Then the surface is metallized followed by trace definition on the photoresist surface. The imaging material could be a photosensitive photoresist, or it could be a dry film pressed to the surface. This method allows a large number of vias to be produced simultaneously at a very low cost. Once the photo resist opening is created, the current practice is to do electroless copper deposition and create an electrically conductive layer inside the via hole. Since the electrically conductive layer in general doesn't adhere to the electrically nonconductive photo resist wall, chemical treatment is necessary to roughen the surface of the via hole before applying the electrically conductive layer. Such chemical treatment also roughens the top surface of the photoresist. For a thin photoresist layer, such roughness on the top surface is undesirable as it increases the chances of shorts between two electrode layers. Further, roughening the via hole increases the photo via hole's size. By the time a photo via hole has been prepared for the electrically conductive layer deposition, the hole size has increased substantially. Since the roughening process is less controllable, the quality of the plated via is not as reproducible. Also, the registration capability is poor at present for trace definition that overlaps the via hole. The technology is not mature enough yet to fully reduce the via pitch even if the via size is very small.
Yet another method uses conductive epoxy resin. After the via hole is created, a conductive epoxy is formed inside the via hole. This method offers via pitch reduction. However, conductive epoxy doesn't adhere well to an electrode if the electrode is made of copper. Moreover, copper can oxidize and create high resistance. To make the contact reliable, inert metals like gold are sometime used to form an interface between conductive epoxy resin and copper electrode, which increases the cost and can present process compatibility problems.